IRWIN AND JOAN JACOBS CENTER FOR COMMUNICATION AND INFORMATION TECHNOLOGIES BENoC: A bus-Enhanced Network on-Chip

Recent research has shown that Network on-chip (NoC) is superior to a bus in terms of power and area for given traffic throughput requirements. Consequently, NoC is expected to be the main interconnect infrastructure in future System on Chip (SoC) and chip multi-processor (CMP). Unlike off-chip networks, VLSI modules are only a few millimeters apart, hence the cost of off-network communication among the network end-points and routers is quite low. Such off-network communication can circumvent weaknesses of the NoC, such as latency of critical signals, complexity and cost of broadcast operations, and operations requiring global knowledge or central control. In this paper we explore the benefits of adding a low latency, customized shared bus as an integral part of the NoC architecture. While the bus is inferior to NoC in terms of data throughput, it possesses two main advantages: First, the bus is inherently capable to broadcast information. Second, the bus has lower and more predictable propagation latency. Therefore, the bus is superior to a multi-hop network for certain transactions such as broadcast of queries, fast delivery of control signals, quick exchange of small data items, network configuration and power management. Moreover, custom properties can be tailored to this particular bus in order to facilitate these specialized tasks. As a result, the Busenhanced NoC (BENoC) is overall more cost-effective than a traditional “busless” NoC. We describe several applications of bus-enhanced networks, such as cache lines lookup and coherency in CMP and efficient management of SoC resources. We present an analytical comparison of the power saving in BENoC versus a network providing similar services. Finally, simulation is used to evaluate the performance of BENoC in a chip multiprocessor system which employs a distributed cache with dynamic non-uniform cache access (DNUCA).